The International Workshop on Power and Timing Modeling, Optimization, and Simulation PATMOS 2002, was the 12th in a series of international workshops 1 previously held in several places in Europe. PATMOS has over the years evolved into a well-established and outstanding series of open European events on power and timing aspects of integrated circuit design. The increased interest, espe- ally in low-power design, has added further momentum to the interest in this workshop. Despite its growth, the workshop can still be considered as a very - cused conference, featuring high-level scienti?c presentations together with open discussions in a free and easy environment. This year, the workshop has been opened to both regular papers and poster presentations. The increasing number of worldwide high-quality submissions is a measure of the global interest of the international scienti?c community in the topics covered by PATMOS. The objective of this workshop is to provide a forum to discuss and inves- gate the emerging problems in the design methodologies and CAD-tools for the new generation of IC technologies. A major emphasis of the technical program is on speed and low-power aspects with particular regard to modeling, char- terization, design, and architectures. The technical program of PATMOS 2002 included nine sessions dedicated to most important and current topics on power and timing modeling, optimization, and simulation. The three invited talks try to give a global overview of the issues in low-power and/or high-performance circuit design.
Erscheinungsdatum: 28.08.2002

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Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation: 12th International Workshop, PATMOS 2002, Seville, Spain, September 11 - 13, 2002 (Lecture Notes in Computer Science)

Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation: 12th International Workshop, PATMOS 2002, Seville, Spain, September ... (Lecture Notes in Computer Science (2451))

Bertrand Hochet; Antonio J Acosta; Manuel J Bellido; International workshop PATMOS 2002

Hochet, Bertrand; Acosta, Antonio J.; Bellido, Manuel J.

PATMOS 2002 (12th 2002 Seville, Spain)

PATMOS (Workshop)

Springer Berlin Heidelberg : Imprint: Springer

Springer Spektrum. in Springer-Verlag GmbH

Steinkopff. in Springer-Verlag GmbH

Springer London, Limited

SpringerLink [host

Springer Nature

Lecture notes in computer science -- 2451. -- Lecture notes in artificial intelligence, Lecture notes in computer science -- 2451, Lecture notes in computer science, Berlin, Germany, 2002

Lecture Notes in Computer Science, 2451, 1st ed. 2002, Berlin, Heidelberg, 2002

Lecture notes in computer science, Berlin [etc, 2002

1 edition, October 3, 2002

Germany, Germany

1, 2002 aug 27

1, 20030802

sm21302064

sm32583229

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Includes bibliographical references.

The First Quartz Electronic Watch....Pages 1-15
An Improved Power Macro-Model for Arithmetic Datapath Components....Pages 16-24
Performance Comparison of VLSI Adders Using Logical Effort....Pages 25-34
MDSP: A High-Performance Low-Power DSP Architecture....Pages 35-44
Impact of Technology in Power-Grid-Induced Noise....Pages 45-54
Exploiting Metal Layer Characteristics for Low-Power Routing....Pages 55-64
Crosstalk Measurement Technique for CMOS ICs....Pages 65-70
Instrumentation Set-up for Instruction Level Power Modeling....Pages 71-80
Low-Power Asynchronous A/D Conversion....Pages 81-91
Optimal Two-Level Delay — Insensitive Implementation of Logic Functions....Pages 92-100
Resonant Multistage Charging of Dominant Capacitances....Pages 101-107
A New Methodology to Design Low-Power Asynchronous Circuits....Pages 108-117
Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library....Pages 118-127
Clocking and Clocked Storage Elements in Multi-GHz Environment....Pages 128-145
Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment....Pages 146-155
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping....Pages 156-166
Robust SAT-Based Search Algorithm for Leakage Power Reduction....Pages 167-177
PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI....Pages 178-187
A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems....Pages 188-197
Clock Distribution Network Optimization under Self-Heating and Timing Constraints....Pages 198-208
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches....Pages 209-218
A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers....Pages 219-228
Output Waveform Evaluation of Basic Pass Transistor Structure....Pages 229-238
An Approach to Energy Consumption Modeling in RC Ladder Circuits....Pages 239-246
Structure Independent Representation of Output Transition Time for CMOS Library....Pages 247-257
A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors....Pages 258-267
Design and Realization of a Low Power Register File Using Energy Model....Pages 268-277
Register File Energy Reduction by Operand Data Reuse....Pages 278-288
Energy-Efficient Design of the Reorder Buffer....Pages 289-299
Trends in Ultralow-Voltage RAM Technology....Pages 300-313
Offine Data Profiling Techniques to Enhance Memory Compression in Embedded Systems....Pages 314-322
Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors....Pages 323-331
Power Consumption Estimation of a C Program for Data-Intensive Applications....Pages 332-341
A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission....Pages 342-352
Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level....Pages 353-362
Low-Power FSMs in FPGA: Encoding Alternatives....Pages 363-370
Synthetic Generation of Events for Address-Event-Representation Communications....Pages 371-379
Reducing Energy Consumption via Low-Cost Value Prediction....Pages 380-389
Dynamic Voltage Scheduling for Real Time Asynchronous Systems....Pages 390-399
Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level....Pages 400-408
Power Efficient Vector Quantization Design Using Pixel Truncation....Pages 409-418
Minimizing Spurious Switching Activities in CMOS Circuits....Pages 419-428
Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates....Pages 429-437
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines....Pages 438-447
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters....Pages 448-457
Probabilistic Power Estimation for Digital Signal Processing Architectures....Pages 458-467
Modeling of Propagation Delay of a First Order Circuit with a Ramp Input....Pages 468-476
Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)....Pages 477-486
Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems....Pages 487-493

<p><p>this Book Constitutes The Refereed Proceedings Of The 12th International Workshop On Power And Timing Modeling, Optimization And Simulation, Patmos 2002, Held In Seville, Spain In September 2002.<br>the 37 Revised Full Papers And 12 Poster Papers Presented Were Carefully Reviewed And Selected From Numerous Submissions. The Papers Are Organized In Topical Sections On Arithmetics, Low-level Modeling And Characterization, Asynchronous And Adiabatic Techniques, Cad Tools And Algorithms, Timing, Gate-level Modeling And Design, And Communications Modeling And Activity Reduction.</p>

This book constitutes the refereed proceedings of the 12th International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2002, held in Seville, Spain in September 2002. The 37 revised full papers and 12 poster papers presented were carefully reviewed and selected from numerous submissions. The papers are organized in topical sections on arithmetics, low-level modeling and characterization, asynchronous and adiabatic techniques, CAD tools and algorithms, timing, gate-level modeling and design, and communications modeling and activity reduction

2014-01-18