A textbook for third and fourth year students in all electrical and computer engineering departments taking electronic circuit courses. . Every chapter features a design problem that tests the problem-solving skills employed by real engineering.

Used book. It only has pencil writing in almost 20 pages...Its in good condition..

Used book. It only has pencil writing in almost 20 pages...Its in good condition..

Used book. It only has pencil writing in almost 20 pages...Its in good condition..

This perfect supplement to Sybex's best-selling Security+ Study Guide was designed for Security+ exam candidates seeking a concise review book to help reinforce the key exam topics. You won't find more concise and economical coverage of the Security+ material. This book's clear-cut, objective-by-objective approach is ideal for last-minute review. The companion CD-ROM includes 2 bonus exams, electronic flashcards, and a searchable key term database. Sybex is proud to serve as a Cornerstone member of the Security+ advisory committee.

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Presents A Balanced Coverage Of Analog And Digital Circuits. This Book Helps Students Develop A Comprehensive Understanding Of The Basic Techniques Of Modern Electronic Circuit Design, Analog And Digital, Discrete And Integrated. It Emphasizes Design Through The Use Of Design Examples And Design Notes. Part I: Solid State Electronics And Devices -- Introduction To Electronics -- Solid-state Electronics -- Solid-state Diodes And Diode Circuits -- Field-effect Transistors -- Bipolar Junction Transistors -- Part Ii: Digital Electronics -- Introduction To Digital Electronics -- Complementary Mos (cmos) Logic Design -- Mos Memory And Storage Circuits -- Bipolar Logic Circuits -- Part Iii: Analog Electronics -- Analog Systems And Ideal Operational Amplifiers -- Nonideal Operational Amplifiers And Feedback Amplifier Stability -- Operational Amplifier Applications -- Small-signal Modeling And Linear Amplification -- Single-transistor Amplifiers -- Differential Amplifiers And Operational Amplifier Design -- Analog Integrated Circuit Design Techniques -- Amplifier Frequency Response -- Transistor Feedback Amplifiers And Oscillators. Richard C. Jaeger, Travis N. Blalock. Includes Bibliographical References And Index.

Richard Jaeger and Travis Blalock present a balanced coverage of analog and digital circuits; students will develop a comprehensive understanding of the basic techniques of modern electronic circuit design, analog and digital, discrete and integrated. A broad spectrum of topics are included in Microelectronic Circuit Design which gives the professor the option to easily select and customize the material to satisfy a two-semester or three-quarter sequence in electronics. Jaeger/Blalock emphasizes design through the use of design examples and design notes. Excellent pedagogical elements include chapter opening vignettes, chapter objectives, “Electronics in Action” boxes, a problem-solving methodology, and "Design Note” boxes. The use of the well-defined problem-solving methodology presented in this text can significantly enhance an engineer’s ability to understand the issues related to design. The design examples assist in building and understanding the design process.

This market-leading textbook continues its standard of excellence and innovation built on the solid pedagogical foundation that instructors expect from Adel S. Sedra and Kenneth C. Smith. All material in the fifth edition of Microelectronic Circuits is thoroughly updated to reflect changes in technology-CMOS technology in particular. These technological changes have shaped the book's organization and topical coverage, making it the most current resource available for teaching tomorrow's engineers how to analyze and design electronic circuits. Features of the Fifth Edition ·Streamlined Organizational Structure: The "must-cover" topics are placed first in each chapter; the more specialized material appears last. The first five chapters, Part I, are organized to form a coherent single-semester introductory course. Similarly, the next five chapters, Part II, present a body of material for a second one-semester course. The final four chapters, Part III, contain significant topics that can be used as enhancements or substitutes for some of the material in earlier chapters as well as resources for project or thesis work. ·MOSFETs and BJTs: Chapter 4 (MOSFETs) and Chapter 5 (BJTs) are completely rewritten. The MOSFET coverage is placed first but the two devices can be covered in any desired order. ·IC MOS and Bipolar Amplifiers: Chapter 6 (Single-Stage Integrated-Circuit Amplifiers) and Chapter 7 (Differential and Multistage Amplifiers) are completely rewritten to introduce IC MOS and bipolar amplifiers in an accessible, systematic way. ·Amplifier Frequency Response: Amplifier frequency response is now presented where needed (a "just-in-time" approach). This includes brief coverage of the frequency responses of the common-source and common-emitter amplifiers in Chapters 4 and 5, respectively. Enhanced Student Support ·A new CD--packaged with every text--includes a free student version of PSpice 9.2 Lite Edition (SPICE simulator) and new industry-based design examples. ·Revised summary sections and many more summary tables are presented. ·Numerous new and varied review exercises and end-of-chapter problems are provided in addition to more SPICE examples with schematic captures. ·An accompanying website (http://www.sedrasmith.org) features: --SPICE Models --Links to industry and academic sites of related interest Enhanced Instructor Support ·An Instructor's Manual with Transparency Masters contains solutions to all in-text exercises and end-of-chapter problems plus hard copy masters of transparency acetates. (978-0-19-517268-3) ·PowerPoint Overheads on CD contain all of the figures with captions from the main text.

1 (p1): PART ONE SOLID STATE ELECTRONIC AND DEVICES 3 (p1-1): CHAPTER 1 INTRODUCTION TO ELECTRONICS 5 (p1-1-1): 1.1 A Brief History of Electronics：From Vacuum Tubes to Giga-Scale Integration 8 (p1-1-2): 1.2 Classifiication of Electronic Signals 9 (p1-1-2-1): 1.2.1 Digital Signals 9 (p1-1-2-2): 1.2.2 Analog Signals 10 (p1-1-2-3): 1.2.3 A/D and D/A Converters—Bridging the Analog and Digital Domains 12 (p1-1-3): 1.3 Notational Conventions 13 (p1-1-4): 1.4 Problem-Solving Approach 15 (p1-1-5): 1.5 Important Concepts from Circuit Theory 15 (p1-1-5-1): 1.5.1 Voltage and Current Division 16 (p1-1-5-2): 1.5.2 Thevenin and Norton Circuit Representations 21 (p1-1-6): 1.6 Frequency Spectrum of Electronic Signals 22 (p1-1-7): 1.7 Amplifiers 23 (p1-1-7-1): 1.7.1 Ideal Operational Amplifiers 25 (p1-1-7-2): 1.7.2 Amplifier Frequency Response 26 (p1-1-8): 1.8 Element Variations in Circuit Design 26 (p1-1-8-1): 1.8.1 Mathematical Modeling of Tolerances 27 (p1-1-8-2): 1.8.2 Worst-Case Analysis 29 (p1-1-8-3): 1.8.3 Monte Carlo Analysis 32 (p1-1-8-4): 1.8.4 Temperature Coeffiicients 34 (p1-1-9): 1.9 Numeric Precision 34 (p1-1-9-1): Summary 35 (p1-1-9-2): Key Terms 36 (p1-1-9-3): References 36 (p1-1-9-4): Additional Reading 37 (p1-1-9-5): Problems 42 (p1-2): CHAPTER 2 SOLID-STATE ELECTRONICS 44 (p1-2-1): 2.1 Solid-State Electronic Materials 45 (p1-2-2): 2.2 Covalent Bond Model 48 (p1-2-3): 2.3 Drift Currents and Mobility in Semiconductors 48 (p1-2-3-1): 2.3.1 Drift Currents 49 (p1-2-3-2): 2.3.2 Mobility 49 (p1-2-3-3): 2.3.3 Velocity Saturation 50 (p1-2-4): 2.4 Resistivity of Intrinsic Silicon 51 (p1-2-5): 2.5 Impurities in Semiconductors 52 (p1-2-5-1): 2.5.1 Donor Impurities in Silicon 52 (p1-2-5-2): 2.5.2 Acceptor Impurities in Silicon 52 (p1-2-6): 2.6 Electron and Hole Concentrations in Doped Semiconductors 53 (p1-2-6-1): 2.6.1 n-Type Material （ND ＞ NA） 54 (p1-2-6-2): 2.6.2 p-Type Material （NA ＞ND） 55 (p1-2-7): 2.7 Mobility and Resistivity in Doped Semiconductors 59 (p1-2-8): 2.8 Diffusion Currents 60 (p1-2-9): 2.9 Total Current 61 (p1-2-10): 2.10 Energy Band Model 61 (p1-2-10-1): 2.10.1 Electron-Hole Pair Generation in an Intrinsic Semiconductor 62 (p1-2-10-2): 2.10.2 Energy Band Model for a Doped Semiconductor 62 (p1-2-10-3): 2.10.3 Compensated Semiconductors 64 (p1-2-11): 2.11 Overview of Integrated Circuit Fabrication 67 (p1-2-11-1): Summary 68 (p1-2-11-2): Key Terms 69 (p1-2-11-3): Reference 69 (p1-2-11-4): Additional Reading 69 (p1-2-11-5): Important Equations 70 (p1-2-11-6): Problems 74 (p1-3): CHAPTER 3 SOLID-STATE DIODES AND DIODE CIRCUITS 75 (p1-3-1): 3.1 The pn Junction Diode 75 (p1-3-1-1): 3.1.1 pn Junction Electrostatics 79 (p1-3-1-2): 3.1.2 Internal Diode Currents 80 (p1-3-2): 3.2 The i-v Characteristics of the Diode 82 (p1-3-3): 3.3 The Diode Equation：A Mathematical Model for the Diode 85 (p1-3-4): 3.4 Diode Characteristics Under Reverse，Zero，and Forward Bias 85 (p1-3-4-1): 3.4.1 Reverse Bias 85 (p1-3-4-2): 3.4.2 Zero Bias 86 (p1-3-4-3): 3.4.3 Forward Bias 89 (p1-3-5): 3.5 Diode Temperature Coefficient 89 (p1-3-6): 3.6 Diodes Under Reverse Bias 90 (p1-3-6-1): 3.6.1 Saturation Current in Real Diodes 91 (p1-3-6-2): 3.6.2 Reverse Breakdown 92 (p1-3-6-3): 3.6.3 Diode Model for the Breakdown Region 92 (p1-3-7): 3.7 pn Junction Capacitance 92 (p1-3-7-1): 3.7.1 Reverse Bias 93 (p1-3-7-2): 3.7.2 Forward Bias 93 (p1-3-8): 3.8 Schottky Barrier Diode 94 (p1-3-9): 3.9 Diode SPICE Model and Layout 96 (p1-3-10): 3.10 Diode Circuit Analysis 96 (p1-3-10-1): 3.10.1 Load-Line Analysis 98 (p1-3-10-2): 3.10.2 Analysis Using the Mathematical Model for the Diode 102 (p1-3-10-3): 3.10.3 The Ideal Diode Model 104 (p1-3-10-4): 3.10.4 Constant Voltage Drop Model 105 (p1-3-10-5): 3.10.5 Model Comparison and Discussion 106 (p1-3-11): 3.11 Multiple-Diode Circuits 109 (p1-3-12): 3.12 Analysis of Diodes Operating in the Breakdown Region 109 (p1-3-12-1): 3.12.1 Load-Line Analysis 109 (p1-3-12-2): 3.12.2 Analysis with the Piecewise Linear Model 110 (p1-3-12-3): 3.12.3 Voltage Regulation 111 (p1-3-12-4): 3.12.4 Analysis Including Zener Resistance 112 (p1-3-12-5): 3.12.5 Line and Load Regulation 113 (p1-3-13): 3.13 Half-Wave Rectifiier Circuits 113 (p1-3-13-1): 3.13.1 Half-Wave Rectifiier with Resistor Load 114 (p1-3-13-2): 3.13.2 Rectifier Filter Capacitor 115 (p1-3-13-3): 3.13.3 Half-Wave Rectifiier with RC Load 116 (p1-3-13-4): 3.13.4 Ripple Voltage and Conduction Interval 118 (p1-3-13-5): 3.13.5 Diode Current 120 (p1-3-13-6): 3.13.6 Surge Current 120 (p1-3-13-7): 3.13.7 Peak-Inverse-Voltage （PIV） Rating 120 (p1-3-13-8): 3.13.8 Diode Power Dissipation 121 (p1-3-13-9): 3.13.9 Half-Wave Rectifier with Negative Output Voltage 123 (p1-3-14): 3.14 Full-Wave Rectifiier Circuits 124 (p1-3-14-1): 3.14.1 Full-Wave Rectifier with Negative Output Voltage 125 (p1-3-15): 3.15 Full-Wave Bridge Rectification 125 (p1-3-16): 3.16 Rectifiier Comparison and Design Tradeoffs 129 (p1-3-17): 3.17 Dynamic Switching Behavior of the Diode 130 (p1-3-18): 3.18 Photo Diodes，Solar Cells，and Light-Emitting Diodes 130 (p1-3-18-1): 3.18.1 Photo Diodes and Photodetectors 131 (p1-3-18-2): 3.18.2 Power Generation from Solar Cells 132 (p1-3-18-3): 3.18.3 Light-Emitting Diodes （LEDs） 133 (p1-3-18-4): Summary 134 (p1-3-18-5): Key Terms 135 (p1-3-18-6): Reference 135 (p1-3-18-7): Additional Reading 135 (p1-3-18-8): Problems 145 (p1-4): CHAPTER 4 FIELD-EFFECT TRANSISTORS 146 (p1-4-1): 4.1 Characteristics of the MOS Capacitor 147 (p1-4-1-1): 4.1.1 Accumulation Region 148 (p1-4-1-2): 4.1.2 Depletion Region 148 (p1-4-1-3): 4.1.3 Inversion Region 148 (p1-4-2): 4.2 The NMOS Transistor 149 (p1-4-2-1): 4.2.1 Qualitative i-v Behavior of the NMOS Transistor 150 (p1-4-2-2): 4.2.2 Triode Region Characteristics of the NMOS Transistor 153 (p1-4-2-3): 4.2.3 On Resistance 154 (p1-4-2-4): 4.2.4 Saturation of the i-v Characteristics 155 (p1-4-2-5): 4.2.5 Mathematical Model in the Saturation （Pinch-Off） Region 157 (p1-4-2-6): 4.2.6 Transconductance 157 (p1-4-2-7): 4.2.7 Channel-Length Modulation 158 (p1-4-2-8): 4.2.8 Transfer Characteristics and Depletion-Mode MOSFETS 159 (p1-4-2-9): 4.2.9 Body Effect or Substrate Sensitivity 161 (p1-4-3): 4.3 PMOS Transistors 163 (p1-4-4): 4.4 MOSFET Circuit Symbols 165 (p1-4-5): 4.5 Capacitances in MOS Transistors 165 (p1-4-5-1): 4.5.1 NMOS Transistor Capacitances in the Triode Region 166 (p1-4-5-2): 4.5.2 Capacitances in the Saturation Region 166 (p1-4-5-3): 4.5.3 Capacitances in Cutoff 167 (p1-4-6): 4.6 MOSFET Modeling in SPICE 169 (p1-4-7): 4.7 MOS Transistor Scaling 169 (p1-4-7-1): 4.7.1 Drain Current 169 (p1-4-7-2): 4.7.2 Gate Capacitance 170 (p1-4-7-3): 4.7.3 Circuit and Power Densities 170 (p1-4-7-4): 4.7.4 Power-Delay Product 171 (p1-4-7-5): 4.7.5 Cutoff Frequency 171 (p1-4-7-6): 4.7.6 High Field Limitations 172 (p1-4-7-7): 4.7.7 Subthreshold Conduction 172 (p1-4-8): 4.8 MOS Transistor Fabrication and Layout Design Rules 173 (p1-4-8-1): 4.8.1 Minimum Feature Size and Alignment Tolerance 173 (p1-4-8-2): 4.8.2 MOS Transistor Layout 176 (p1-4-9): 4.9 Biasing the NMOS Field-Effect Transistor 176 (p1-4-9-1): 4.9.1 Why Do We Need Bias？ 178 (p1-4-9-2): 4.9.2 Constant Gate-Source Voltage Bias 181 (p1-4-9-3): 4.9.3 Load Line Analysis for the Q-Point 182 (p1-4-9-4): 4.9.4 Four-Resistor Biasing 188 (p1-4-10): 4.10 Biasing the PMOS Field-Effect Transistor 190 (p1-4-11): 4.11 The Junction Field-Effect Transistor （IFET） 191 (p1-4-11-1): 4.11.1 The JFET with Bias Applied 191 (p1-4-11-2): 4.11.2 JFET Channel with Drain-Source Bias 193 (p1-4-11-3): 4.11.3 n-Channel JFET i-v Characteristics 195 (p1-4-11-4): 4.11.4 The p-Channel JFET 195 (p1-4-11-5): 4.11.5 Circuit Symbols and JFET Model Summary 196 (p1-4-11-6): 4.11.6 JFET Capacitances 197 (p1-4-12): 4.12 JFET Modeling in SPICE 198 (p1-4-13): 4.13 Biasing the JFET and Depletion-Mode MOSFET 200 (p1-4-13-1): Summary 202 (p1-4-13-2): Key Terms 203 (p1-4-13-3): References 204 (p1-4-13-4): Problems 217 (p1-5): CHAPTER 5 BIPOLAR JUNCTION TRANSISTORS 218 (p1-5-1): 5.1 Physical Structure of the Bipolar Transistor 219 (p1-5-2): 5.2 The Transport Model for the npn Transistor 220 (p1-5-2-1): 5.2.1 Forward Characteristics 222 (p1-5-2-2): 5.2.2 Reverse Characteristics 223 (p1-5-2-3): 5.2.3 The Complete Transport Model Equations for Arbitrary Bias Conditions 225 (p1-5-3): 5.3 The pnp Transistor 227 (p1-5-4): 5.4 Equivalent Circuit Representations for the Transport Models 228 (p1-5-5): 5.5 The i-v Characteristics of the Bipolar Transistor 228 (p1-5-5-1): 5.5.1 Output Characteristics 229 (p1-5-5-2): 5.5.2 Transfer Characteristics 230 (p1-5-6): 5.6 The Operating Regions of the Bipolar Transistor 231 (p1-5-7): 5.7 Transport Model Simplifiications 231 (p1-5-7-1): 5.7.1 Simplified Model for the Cutoff Region 233 (p1-5-7-2): 5.7.2 Model Simplifications for the Forward-Active Region 239 (p1-5-7-3): 5.7.3 Diodes in Bipolar Integrated Circuits 240 (p1-5-7-4): 5.7.4 Simplifiied Model for the Reverse-Active Region 242 (p1-5-7-5): 5.7.5 Modeling Operation in the Saturation Region 245 (p1-5-8): 5.8 Nonideal Behavior of the Bipolar Transistor 246 (p1-5-8-1): 5.8.1 Junction Breakdown Voltages 246 (p1-5-8-2): 5.8.2 Minority-Carrier Transport in the Base Region 247 (p1-5-8-3): 5.8.3 Base Transit Time 249 (p1-5-8-4): 5.8.4 Diffusion Capacitance 250 (p1-5-8-5): 5.8.5 Frequency Dependence of the Common-Emitter Current Gain 250 (p1-5-8-6): 5.8.6 The Early Effect and Early Voltage 251 (p1-5-8-7): 5.8.7 Modeling the Early Effect 251 (p1-5-8-8): 5.8.8 Origin of the Early Effect 252 (p1-5-9): 5.9 Transconductance 253 (p1-5-10): 5.10 Bipolar Technology and SPICE Model 253 (p1-5-10-1): 5.10.1 Qualitative Description 254 (p1-5-10-2): 5.10.2 SPICE Model Equations 255 (p1-5-10-3): 5.10.3 High-Performance Bipolar Transistors 256 (p1-5-11): 5.11 Practical Bias Circuits for the BJT 258 (p1-5-11-1): 5.11.1 Four-Resistor Bias Network 260 (p1-5-11-2): 5.11.2 Design Objectives for the Four-Resistor Bias Network 266 (p1-5-11-3): 5.11.3 Iterative Analysis of the Four-Resistor Bias Circuit 266 (p1-5-12): 5.12 Tolerances in Bias Circuits 267 (p1-5-12-1): 5.12.1 Worst-Case Analysis 269 (p1-5-12-2): 5.12.2 Monte Carlo Analysis 272 (p1-5-12-3): Summary 274 (p1-5-12-4): Key Terms 274 (p1-5-12-5): References 275 (p1-5-12-6): Problems 285 (p2): PART TWO DIGITAL ELECTRONICS 287 (p2-1): CHAPTER 6 INTRODUCTION TO DIGITAL ELECTRONICS 289 (p2-1-1): 6.1 Ideal Logic Gates 289 (p2-1-2): 6.2 Logic Level Definitions and Noise Margins 291 (p2-1-2-1): 6.2.1 Logic Voltage Levels 291 (p2-1-2-2): 6.2.2 Noise Margins 292 (p2-1-2-3): 6.2.3 Logic Gate Design Goals 293 (p2-1-3): 6.3 Dynamic Response of Logic Gates 293 (p2-1-3-1): 6.3.1 Rise Time and Fall Time 294 (p2-1-3-2): 6.3.2 Propagation Delay 294 (p2-1-3-3): 6.3.3 Power-Delay Product 295 (p2-1-4): 6.4 Review of Boolean Algebra 297 (p2-1-5): 6.5 NMOS Logic Design 298 (p2-1-5-1): 6.5.1 NMOS Inverter with Resistive Load 299 (p2-1-5-2): 6.5.2 Design of the W/L Ratio of Ms 300 (p2-1-5-3): 6.5.3 Load Resistor Design 300 (p2-1-5-4): 6.5.4 Load-Line Visualization 302 (p2-1-5-5): 6.5.5 On-Resistance of the Switching Device 303 (p2-1-5-6): 6.5.6 Noise Margin Analysis 303 (p2-1-5-7): 6.5.7 Calculation of V IL and VOH 304 (p2-1-5-8): 6.5.8 Calculation of V I H and VOL 305 (p2-1-5-9): 6.5.9 Load Resistor Problems 306 (p2-1-6): 6.6 Transistor Alternatives to the Load Resistor 307 (p2-1-6-1): 6.6.1 The NMOS Saturated Load Inverter 315 (p2-1-6-2): 6.6.2 NMOS Inverter with a Linear Load Device 316 (p2-1-6-3): 6.6.3 NMOS Inverter with a Depletion-Mode Load 319 (p2-1-6-4): 6.6.4 Static Design of the Pseudo NMOS Inverter 323 (p2-1-7): 6.7 NMOS Inverter Summary and Comparison 324 (p2-1-8): 6.8 NMOS NAND and NOR Gates 325 (p2-1-8-1): 6.8.1 NOR Gates 326 (p2-1-8-2): 6.8.2 NAND Gates 327 (p2-1-8-3): 6.8.3 NOR and NAND Gate Layouts in NMOS Depletion-Mode Technology 328 (p2-1-9): 6.9 Complex NMOS Logic Design 333 (p2-1-10): 6.10 Power Dissipation 333 (p2-1-10-1): 6.10.1 Static Power Dissipation 334 (p2-1-10-2): 6.10.2 Dynamic Power Dissipation 335 (p2-1-10-3): 6.10.3 Power Scaling in MOS Logic Gates 337 (p2-1-11): 6.11 Dynamic Behavior of MOS Logic Gates 337 (p2-1-11-1): 6.11.1 Capacitances in Logic Circuits 338 (p2-1-11-2): 6.11.2 Dynamic Response of the NMOS Inverter with a Resistive Load 343 (p2-1-11-3): 6.11.3 Pseudo NMOS Inverter 344 (p2-1-11-4): 6.11.4 A Final Comparison of NMOS Inverter Delays 346 (p2-1-11-5): 6.11.5 Scaling Based Upon Reference Circuit Simulation 346 (p2-1-11-6): 6.11.6 Ring Oscillator Measurement of Intrinsic Gate Delay 347 (p2-1-11-7): 6.11.7 Unloaded Inverter Delay 349 (p2-1-12): 6.12 PMOS Logic 349 (p2-1-12-1): 6.12.1 PMOS Inverters 352 (p2-1-12-2): 6.12.2 NOR and NAND Gates 352 (p2-1-12-3): Summary 354 (p2-1-12-4): Key Terms 355 (p2-1-12-5): References 355 (p2-1-12-6): Additional Reading 355 (p2-1-12-7): Problems 367 (p2-2): CHAPTER 7 COMPLEMENTARY MOS （CMOS） LOGIC DESIGN 368 (p2-2-1): 7.1 CMOS Inverter Technology 370 (p2-2-1-1): 7.1.1 CMOS Inverter Layout 370 (p2-2-2): 7.2 Static Characteristics of the CMOS Inverter 371 (p2-2-2-1): 7.2.1 CMOS Voltage Transfer Characteristics 373 (p2-2-2-2): 7.2.2 Noise Margins for the CMOS Inverter 375 (p2-2-3): 7.3 Dynamic Behavior of the CMOS Inverter 375 (p2-2-3-1): 7.3.1 Propagation Delay Estimate 377 (p2-2-3-2): 7.3.2 Rise and Fall Times 377 (p2-2-3-3): 7.3.3 Performance Scaling 379 (p2-2-3-4): 7.3.4 Delay of Cascaded Inverters 380 (p2-2-4): 7.4 Power Dissipation and Power Delay Product in CMOS 380 (p2-2-4-1): 7.4.1 Static Power Dissipation 381 (p2-2-4-2): 7.4.2 Dynamic Power Dissipation 382 (p2-2-4-3): 7.4.3 Power-Delay Product 384 (p2-2-5): 7.5 CMOS NOR and NAND Gates 384 (p2-2-5-1): 7.5.1 CMOS NOR Gate 387 (p2-2-5-2): 7.5.2 CMOS NAND Gates 388 (p2-2-6): 7.6 Design of Complex Gates in CMOS 393 (p2-2-7): 7.7 Minimum Size Gate Design and Performance 395 (p2-2-8): 7.8 Dynamic Domino CMOS Logic 397 (p2-2-9): 7.9 Cascade Buffers 397 (p2-2-9-1): 7.9.1 Cascade Buffer Delay Model 398 (p2-2-9-2): 7.9.2 Optimum Number of Stages 400 (p2-2-10): 7.10 The CMOS Transmission Gate 401 (p2-2-11): 7.11 CMOS Latchup 404 (p2-2-11-1): Summary 405 (p2-2-11-2): Key Terms 406 (p2-2-11-3): References 406 (p2-2-11-4): Problems 416 (p2-3): CHAPTER 8 MOS MEMORY AND STORAGE CIRCUITS 417 (p2-3-1): 8.1 Random Access Memory 417 (p2-3-1-1): 8.1.1 Random Access Memory （RAM） Architecture 418 (p2-3-1-2): 8.1.2 A 256-Mb Memory Chip 419 (p2-3-2): 8.2 Static Memory Cells 422 (p2-3-2-1): 8.2.1 Memory Cell Isolation and Access—The 6-T Cell 422 (p2-3-2-2): 8.2.2 The Read Operation 426 (p2-3-2-3): 8.2.3 Writing Data into the 6-T Cell 428 (p2-3-3): 8.3 Dynamic Memory Cells 430 (p2-3-3-1): 8.3.1 The One-Transistor Cell 430 (p2-3-3-2): 8.3.2 Data Storage in the 1-T Cell 431 (p2-3-3-3): 8.3.3 Reading Data from the 1-T Cell 433 (p2-3-3-4): 8.3.4 The Four-Transistor Cell 434 (p2-3-4): 8.4 Sense Amplifiers 434 (p2-3-4-1): 8.4.1 A Sense Amplifier for the 6-T Cell 436 (p2-3-4-2): 8.4.2 A Sense Amplifier for the 1-T Cell 438 (p2-3-4-3): 8.4.3 The Boosted Wordline Circuit 438 (p2-3-4-4): 8.4.4 Clocked CMOS Sense Amplifiiers 440 (p2-3-5): 8.5 Address Decoders 440 (p2-3-5-1): 8.5.1 NOR Decoder 440 (p2-3-5-2): 8.5.2 NAND Decoder 443 (p2-3-5-3): 8.5.3 Decoders in Domino CMOS Logic 443 (p2-3-5-4): 8.5.4 Pass-Transistor Column Decoder 444 (p2-3-6): 8.6 Read-Only Memory （ROM） 447 (p2-3-7): 8.7 Flip-Flops 449 (p2-3-7-1): 8.7.1 RS Flip-Flop 450 (p2-3-7-2): 8.7.2 The D-Latch Using Transmission Gates 450 (p2-3-7-3): 8.7.3 A Master-Slave D Flip-Flop 451 (p2-3-7-4): Summary 452 (p2-3-7-5): Key Terms 452 (p2-3-7-6): References 453 (p2-3-7-7): Problems 460 (p2-4): CHAPTER 9 BIPOLAR LOGIC CIRCUITS 461 (p2-4-1): 9.1 The Current Switch （Emitter-Coupled Pair） 462 (p2-4-1-1): 9.1.1 Mathematical Model for Static Behavior of the Current Switch 463 (p2-4-1-2): 9.1.2 Current Switch Analysis for V I ＞ VREF 464 (p2-4-1-3): 9.1.3 Current Switch Analysis for V I ＜ VREF 464 (p2-4-2): 9.2 The Emitter-Coupled Logic （ECL） Gate 465 (p2-4-2-1): 9.2.1 ECL Gate with vI = VH 466 (p2-4-2-2): 9.2.2 ECL Gate with vI = VL 466 (p2-4-2-3): 9.2.3 Input Current of the ECL Gate 466 (p2-4-2-4): 9.2.4 ECL Summary 467 (p2-4-3): 9.3 Noise Margin Analysis for the ECL Gate 467 (p2-4-3-1): 9.3.1 VI L，VOH，VI H，and VOL 468 (p2-4-3-2): 9.3.2 Noise Margins 469 (p2-4-4): 9.4 Current Source Implementation 471 (p2-4-5): 9.5 The ECL OR-NOR Gate 473 (p2-4-6): 9.6 The Emitter Follower 474 (p2-4-6-1): 9.6.1 Emitter Follower with a Load Resistor 476 (p2-4-7): 9.7 “Emitter Dotting” or “Wired-OR” Logic 477 (p2-4-7-1): 9.7.1 Parallel Connection of Emitter-Follower Outputs 477 (p2-4-7-2): 9.7.2 The Wired-OR Logic Function 477 (p2-4-8): 9.8 ECL Power-Delay Characteristics 477 (p2-4-8-1): 9.8.1 Power Dissipation 479 (p2-4-8-2): 9.8.2 Gate Delay 480 (p2-4-8-3): 9.8.3 Power-Delay Product 481 (p2-4-9): 9.9 Current Mode Logic 481 (p2-4-9-1): 9.9.1 CML Logic Gates 482 (p2-4-9-2): 9.9.2 CML Logic Levels 482 (p2-4-9-3): 9.9.3 VEE Supply Voltage 483 (p2-4-9-4): 9.9.4 Higher-Level CML 484 (p2-4-9-5): 9.9.5 CML Power Reduction 485 (p2-4-9-6): 9.9.6 NMOS CML 487 (p2-4-10): 9.10 The Saturating Bipolar Inverter 488 (p2-4-10-1): 9.10.1 Static Inverter Characteristics 488 (p2-4-10-2): 9.10.2 Saturation Voltage of the Bipolar Transistor 491 (p2-4-10-3): 9.10.3 Load-Line Visualization 491 (p2-4-10-4): 9.10.4 Switching Characteristics of the Saturated BJT 494 (p2-4-11): 9.11 A Transistor-Transistor Logic （TTL） Prototype 494 (p2-4-11-1): 9.11.1 TTL Inverter for vI = VL 495 (p2-4-11-2): 9.11.2 TTL Inverter for vI = VH 496 (p2-4-11-3): 9.11.3 Power in the Prototype TTL Gate 496 (p2-4-11-4): 9.11.4 VIH，VIL，and Noise Margins for the TTL Prototype 498 (p2-4-11-5): 9.11.5 Prototype Inverter Summary 498 (p2-4-11-6): 9.11.6 Fanout Limitations of the TTL Prototype 500 (p2-4-12): 9.12 The Standard 7400 Series TTL Inverter 500 (p2-4-12-1): 9.12.1 Analysis for V I = VL 501 (p2-4-12-2): 9.12.2 Analysis for V I = VH 503 (p2-4-12-3): 9.12.3 Power Consumption 503 (p2-4-12-4): 9.12.4 TTL Propagation Delay and Power-Delay Product 503 (p2-4-12-5): 9.12.5 TTL Voltage Transfer Characteristic and Noise Margins 504 (p2-4-12-6): 9.12.6 Fanout Limitations of Standard TTL 504 (p2-4-13): 9.13 Logic Functions in TTL 505 (p2-4-13-1): 9.13.1 Multi-Emitter Input Transistors 505 (p2-4-13-2): 9.13.2 TTL NAND Gates 506 (p2-4-13-3): 9.13.3 Input Clamping Diodes 506 (p2-4-14): 9.14 Schottky-Clamped TTL 508 (p2-4-15): 9.15 Comparison of the Power-Delay Products of ECL and TTL 508 (p2-4-16): 9.16 BiCMOS Logic 509 (p2-4-16-1): 9.16.1 BiCMOS Buffers 511 (p2-4-16-2): 9.16.2 BiNMOS Inverters 513 (p2-4-16-3): 9.16.3 BiCMOS Logic Gates 513 (p2-4-16-4): Summary 515 (p2-4-16-5): Key Terms 515 (p2-4-16-6): References 515 (p2-4-16-7): Additional Reading 516 (p2-4-16-8): Problems 527 (p3): PART THREE ANALOG ELECTRONICS 529 (p3-1): CHAPTER10 ANALOG SYSTEMS AND IDEAL OPERATIONAL AMPLIFIERS 530 (p3-1-1): 10.1 An Example of an Analog Electronic System 531 (p3-1-2): 10.2 Amplifiication 532 (p3-1-2-1): 10.2.1 Voltage Gain 533 (p3-1-2-2): 10.2.2 Current Gain 533 (p3-1-2-3): 10.2.3 Power Gain 534 (p3-1-2-4): 10.2.4 The Decibel Scale 537 (p3-1-3): 10.3 Two-Port Models for Amplifiiers 537 (p3-1-3-1): 10.3.1 The g-parameters 541 (p3-1-4): 10.4 Mismatched Source and Load Resistances 544 (p3-1-5): 10.5 Introduction to Operational Amplifiers 544 (p3-1-5-1): 10.5.1 The Differential Amplifier 545 (p3-1-5-2): 10.5.2 Differential Amplifier Voltage Transfer Characteristic 545 (p3-1-5-3): 10.5.3 Voltage Gain 548 (p3-1-6): 10.6 Distortion in Amplifiers 549 (p3-1-7): 10.7 Differential Amplifier Model 551 (p3-1-8): 10.8 Ideal Differential and Operational Amplifiers 551 (p3-1-8-1): 10.8.1 Assumptions for Ideal Operational Amplifier Analysis 552 (p3-1-9): 10.9 Analysis of Circuits Containing Ideal Operational Amplifiiers 553 (p3-1-9-1): 10.9.1 The Inverting Amplifiier 556 (p3-1-9-2): 10.9.2 The Transresistance Amplifiier—A Current-to-Voltage Converter 558 (p3-1-9-3): 10.9.3 The Noninverting Amplifier 561 (p3-1-9-4): 10.9.4 The Unity-Gain Buffer，or Voltage Follower 563 (p3-1-9-5): 10.9.5 The Summing Amplifiier 565 (p3-1-9-6): 10.9.6 The Difference Amplifier 568 (p3-1-10): 10.10 Frequency-Dependent Feedback 568 (p3-1-10-1): 10.10.1 Bode Plots 568 (p3-1-10-2): 10.10.2 The Low-Pass Amplifier 572 (p3-1-10-3): 10.10.3 The High-Pass Amplifier 575 (p3-1-10-4): 10.10.4 Band-Pass Amplifiers 578 (p3-1-10-5): 10.10.5 An Active Low-Pass Filter 581 (p3-1-10-6): 10.10.6 An Active High-Pass Filter 582 (p3-1-10-7): 10.10.7 The Integrator 586 (p3-1-10-8): 10.10.8 The Differentiator 586 (p3-1-10-9): Summary 588 (p3-1-10-10): Key Terms 588 (p3-1-10-11): References 589 (p3-1-10-12): Additional Reading 589 (p3-1-10-13): Problems 600 (p3-2): CHAPTER 11 NONIDEAL OPERATIONAL AMPLIFIERS AND FEEDBACK AMPLIFIER STABILITY 601 (p3-2-1): 11.1 Classic Feedback Systems 602 (p3-2-1-1): 11.1.1 Closed-Loop Gain Analysis 602 (p3-2-1-2): 11.1.2 Gain Error 603 (p3-2-2): 11.2 Analysis of Circuits Containing Nonideal Operational Amplifiers 603 (p3-2-2-1): 11.2.1 Finite Open-Loop Gain 606 (p3-2-2-2): 11.2.2 Nonzero Output Resistance 610 (p3-2-2-3): 11.2.3 Finite Input Resistance 614 (p3-2-2-4): 11.2.4 Summary of Nonideal Inverting and Noninverting Amplifiiers 615 (p3-2-3): 11.3 Series and Shunt Feedback Circuits 615 (p3-2-3-1): 11.3.1 Feedback Amplifier Categories 616 (p3-2-3-2): 11.3.2 Voltage Amplifiers—Series-Shunt Feedback 616 (p3-2-3-3): 11.3.3 Transimpedance Amplifiers—Shunt-Shunt Feedback 616 (p3-2-3-4): 11.3.4 Current Amplifiiers—Shunt-Series Feedback 616 (p3-2-3-5): 11.3.5 Transconductance Amplifiiers—Series-Series Feedback 616 (p3-2-4): 11.4 Unifiied Approach to Feedback Amplifier Gain Calculation 617 (p3-2-4-1): 11.4.1 Closed-Loop Gain Analysis 617 (p3-2-4-2): 11.4.2 Resistance Calculation Using Blackman’S Theorem 617 (p3-2-5): 11.5 Series-Shunt Feedback-Voltage Amplifiiers 618 (p3-2-5-1): 11.5.1 Closed-Loop Gain Calculation 618 (p3-2-5-2): 11.5.2 Input Resistance Calculation 619 (p3-2-5-3): 11.5.3 Output Resistance Calculation 620 (p3-2-5-4): 11.5.4 Series-Shunt Feedback Amplifiier Summary 624 (p3-2-6): 11.6 Shunt-Shunt Feed back—Transresistance Amplifiers 625 (p3-2-6-1): 11.6.1 Closed-Loop Gain Calculation 625 (p3-2-6-2): 11.6.2 Input Resistance Calculation 625 (p3-2-6-3): 11.6.3 Output Resistance Calculation 626 (p3-2-6-4): 11.6.4 Shunt-Shunt Feedback Amplifier Summary 629 (p3-2-7): 11.7 Series-Series Feedback —Transconductance Amplifiiers 630 (p3-2-7-1): 11.7.1 Closed-Loop Gain Calculation 630 (p3-2-7-2): 11.7.2 Input Resistance Calculation 631 (p3-2-7-3): 11.7.3 Output Resistance Calculation 631 (p3-2-7-4): 11.7.4 Series-Series Feedback Amplifiier Summary 633 (p3-2-8): 11.8 Shunt-Series Feedback—Current Amplifiers 634 (p3-2-8-1): 11.8.1 Closed-Loop Gain Calculation 635 (p3-2-8-2): 11.8.2 Input Resistance Calculation 635 (p3-2-8-3): 11.8.3 Output Resistance Calculation 635 (p3-2-8-4): 11.8.4 Series-Series Feedback Amplifiier Summary 638 (p3-2-9): 11.9 Finding the Loop Gain Using Successive Voltage and Current Injection 641 (p3-2-9-1): 11.9.1 Simplifications 641 (p3-2-10): 11.10 Distortion Reduction Through the Use of Feedback 642 (p3-2-11): 11.11 DC Error Sources and Output Range Limitations 643 (p3-2-11-1): 11.11.1 Input-Offset Voltage 644 (p3-2-11-2): 11.11.2 Offset-Voltage Adjustment 645 (p3-2-11-3): 11.11.3 Input-Bias and Offset Currents 647 (p3-2-11-4): 11.11.4 Output Voltage and Current Limits 650 (p3-2-12): 11.12 Common-Mode Rejection and Input Resistance 650 (p3-2-12-1): 11.12.1 Finite Common-Mode Rejection Ratio 651 (p3-2-12-2): 11.12.2 Why Is CMRR Important？ 654 (p3-2-12-3): 11.12.3 Voltage-Follower Gain Error Due to CMRR 656 (p3-2-12-4): 11.12.4 Common-Mode Input Resistance 657 (p3-2-12-5): 11.12.5 An Alternate Interpretation of CMRR 657 (p3-2-12-6): 11.12.6 Power Supply Rejection Ratio 659 (p3-2-13): 11.13 Frequency Response and Bandwidth of Operational Amplifiers 661 (p3-2-13-1): 11.13.1 Frequency Response of the NoninvertingAmplifiier 664 (p3-2-13-2): 11.13.2 Inverting Amplifiier Frequency Response 666 (p3-2-13-3): 11.13.3 Using Feedback to Control Frequency Response 668 (p3-2-13-4): 11.13.4 Large-Signal Limitations—Slew Rate and Full-Power Bandwidth 669 (p3-2-13-5): 11.13.5 Macro Model for Operational Amplifier Frequency Response 670 (p3-2-13-6): 11.13.6 Complete Op Amp Macro Models in SPICE 670 (p3-2-13-7): 11.13.7 Examples of Commercial General-Purpose Operational Amplifiiers 671 (p3-2-14): 11.14 Stability of Feedback Amplifiers 671 (p3-2-14-1): 11.14.1 The Nyquist Plot 672 (p3-2-14-2): 11.14.2 First-Order Systems 673 (p3-2-14-3): 11.14.3 Second-Order Systems and Phase Margin 674 (p3-2-14-4): 11.14.4 Step Response and Phase Margin 677 (p3-2-14-5): 11.14.5 Third-Order Systems and Gain Margin 678 (p3-2-14-6): 11.14.6 Determining Stability from the Bode Plot 682 (p3-2-14-7): Summary 684 (p3-2-14-8): Key Terms 684 (p3-2-14-9): References 685 (p3-2-14-10): Problems 697 (p3-3): CHAPTER 12 OPERATIONAL AMPLIFIER APPLICATIONS 698 (p3-3-1): 12.1 Cascaded Amplifiiers 698 (p3-3-1-1): 12.1.1 Two-Port Representations 700 (p3-3-1-2): 12.1.2 Amplifiier Terminology Review 703 (p3-3-1-3): 12.1.3 Frequency Response of Cascaded Amplifiiers 711 (p3-3-2): 12.2 The Instrumentation Amplifiier 714 (p3-3-3): 12.3 Active Filters 714 (p3-3-3-1): 12.3.1 Low-Pass Filter 718 (p3-3-3-2): 12.3.2 A High-Pass Filter with Gain 720 (p3-3-3-3): 12.3.3 Band-Pass Filter 722 (p3-3-3-4): 12.3.4 The Tow-Thomas Biquad 726 (p3-3-3-5): 12.3.5 Sensitivity 727 (p3-3-3-6): 12.3.6 Magnitude and Frequency Scaling 728 (p3-3-4): 12.4 Switched-Capacitor Circuits 728 (p3-3-4-1): 12.4.1 A Switched-Capacitor Integrator 730 (p3-3-4-2): 12.4.2 Noninverting SC Integrator 732 (p3-3-4-3): 12.4.3 Switched-Capacitor Filters 733 (p3-3-5): 12.5 Digital-to-Analog Conversion 733 (p3-3-5-1): 12.5.1 D/A Converter Fundamentals 734 (p3-3-5-2): 12.5.2 D/A Converter Errors 737 (p3-3-5-3): 12.5.3 Digital-to-Analog Converter Circuits 740 (p3-3-6): 12.6 Analog-to-Digital Conversion 741 (p3-3-6-1): 12.6.1 A/D Converter Fundamentals 742 (p3-3-6-2): 12.6.2 Analog-to-Digital Converter Errors 743 (p3-3-6-3): 12.6.3 Basic A/D Conversion Techniques 754 (p3-3-7): 12.7 Oscillators 754 (p3-3-7-1): 12.7.1 The Barkhausen Criteria for Oscillation 755 (p3-3-7-2): 12.7.2 Oscillators Employing Frequency-Selective RC Networks 760 (p3-3-8): 12.8 Nonlinear Circuit Applications 760 (p3-3-8-1): 12.8.1 A Precision Half-Wave Rectifiier 761 (p3-3-8-2): 12.8.2 Nonsaturating Precision-Rectifiier Circuit 763 (p3-3-9): 12.9 Circuits Using Positive Feedback 763 (p3-3-9-1): 12.9.1 The Comparator and Schmitt Trigger 765 (p3-3-9-2): 12.9.2 The Astable Multivibrator 766 (p3-3-9-3): 12.9.3 The Monostable Multivibrator or One Shot 770 (p3-3-9-4): Summary 772 (p3-3-9-5): Key Terms 773 (p3-3-9-6): Additional Reading 773 (p3-3-9-7): Problems 786 (p3-4): CHAPTER 13 SMALL-SIGNAL MODELING AND LINEAR AMPLIFICATION 787 (p3-4-1): 13.1 The Transistor as an Amplifier 788 (p3-4-1-1): 13.1.1 The BJT Amplifier 789 (p3-4-1-2): 13.1.2 The MOSFET Amplifier 790 (p3-4-2): 13.2 Coupling and Bypass Capacitors 792 (p3-4-3): 13.3 Circuit Analysis Using dc and ac Equivalent Circuits 792 (p3-4-3-1): 13.3.1 Menu for dc and ac Analysis 796 (p3-4-4): 13.4 Introduction to Small-Signal Modeling 796 (p3-4-4-1): 13.4.1 Graphical Interpretation of the Small-Signal Behavior of the Diode 797 (p3-4-4-2): 13.4.2 Small-Signal Modeling of the Diode 799 (p3-4-5): 13.5 Small-Signal Models for Bipolar Junction Transistors 801 (p3-4-5-1): 13.5.1 The Hybrid-Pi Model 802 (p3-4-5-2): 13.5.2 Graphical Interpretation of the Transconductance 802 (p3-4-5-3): 13.5.3 Small-Signal Current Gain 803 (p3-4-5-4): 13.5.4 The Intrinsic Voltage Gain of the BJT 804 (p3-4-5-5): 13.5.5 Equivalent Forms of the Small-Signal Model 805 (p3-4-5-6): 13.5.6 Simplifiied Hybrid Pi Model 805 (p3-4-5-7): 13.5.7 Definition of a Small Signal for the Bipolar Transistor 807 (p3-4-5-8): 13.5.8 Small-Signal Model for the pnp Transistor 807 (p3-4-5-9): 13.5.9 ac Analysis Versus Transient Analysis in SPICE 808 (p3-4-6): 13.6 The Common-Emitter （C-E） Amplifier 809 (p3-4-6-1): 13.6.1 Terminal Voltage Gain 809 (p3-4-6-2): 13.6.2 Input Resistance 810 (p3-4-6-3): 13.6.3 Signal Source Voltage Gain 810 (p3-4-7): 13.7 Important Limits and Model Simplifications 810 (p3-4-7-1): 13.7.1 A Design Guide for the Common-Emitter Amplifier 812 (p3-4-7-2): 13.7.2 Upper Bound on the Common-Emitter Gain 812 (p3-4-7-3): 13.7.3 Small-Signal Limit for the Common-emitter Amplifier 815 (p3-4-8): 13.8 Small-Signal Models for Field-Effect Transistors 815 (p3-4-8-1): 13.8.1 Small-Signal Model for the MOSFET 817 (p3-4-8-2): 13.8.2 Intrinsic Voltage Gain of the MOSFET 817 (p3-4-8-3): 13.8.3 Defiinition of Small-Signal Operation for the MOSFET 818 (p3-4-8-4): 13.8.4 Body Effect in the Four-Terminal MOSFET 819 (p3-4-8-5): 13.8.5 Small-Signal Model for the PMOS Transistor 820 (p3-4-8-6): 13.8.6 Small-Signal Model for the Junction Field-Effect Transistor 821 (p3-4-9): 13.9 Summary and Comparison of the Small-Signal Models of the BJT and FET 824 (p3-4-10): 13.10 The Common-Source Amplifier 825 (p3-4-10-1): 13.10.1 Common-Source Terminal Voltage Gain 825 (p3-4-10-2): 13.10.2 Signal Source Voltage Gain for the Common-Source Amplifier 826 (p3-4-10-3): 13.10.3 A Design Guide for the Common-Source Amplifier 827 (p3-4-10-4): 13.10.4 Small-Signal Limit for the Common-Source Amplifier 829 (p3-4-10-5): 13.10.5 Input Resistances of the Common-Emitter and Common-Source Amplifiers 832 (p3-4-10-6): 13.10.6

This market-leading textbook continues its standard of excellence and innovation built on the solid pedagogical foundation that instructors expect from Adel S. Sedra and Kenneth C. Smith. All material in the fifth edition of Microelectronic Circuits is thoroughly updated to reflect changes in technology-CMOS technology in particular. These technological changes have shaped the book's organization and topical coverage, making it the most current resource available for teaching tomorrow's engineers how to analyze and design electronic circuits. Features of the Fifth Edition ·Streamlined Organizational Structure: The "must-cover" topics are placed first in each chapter; the more specialized material appears last. The first five chapters, Part I, are organized to form a coherent single-semester introductory course. Similarly, the next five chapters, Part II, present a body of material for a second one-semester course. The final four chapters, Part III, contain significant topics that can be used as enhancements or substitutes for some of the material in earlier chapters as well as resources for project or thesis work. ·MOSFETs and BJTs: Chapter 4 (MOSFETs) and Chapter 5 (BJTs) are completely rewritten. The MOSFET coverage is placed first but the two devices can be covered in any desired order. ·IC MOS and Bipolar Amplifiers: Chapter 6 (Single-Stage Integrated-Circuit Amplifiers) and Chapter 7 (Differential and Multistage Amplifiers) are completely rewritten to introduce IC MOS and bipolar amplifiers in an accessible, systematic way. ·Amplifier Frequency Response: Amplifier frequency response is now presented where needed (a "just-in-time" approach). This includes brief coverage of the frequency responses of the common-source and common-emitter amplifiers in Chapters 4 and 5, respectively. Enhanced Student Support ·A new CD--packaged with every text--includes a free student version of PSpice 9.2 Lite Edition (SPICE simulator) and new industry-based design examples. ·Revised summary sections and many more summary tables are presented. ·Numerous new and varied review exercises and end-of-chapter problems are provided in addition to more SPICE examples with schematic captures. ·An accompanying website (http://www.sedrasmith.org) features: --SPICE Models --Links to industry and academic sites of related interest Enhanced Instructor Support ·An Instructor's Manual with Transparency Masters contains solutions to all in-text exercises and end-of-chapter problems plus hard copy masters of transparency acetates. (978-0-19-517268-3) ·PowerPoint Overheads on CD contain all of the figures with captions from the main text.

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